Since 2001, WIZnet released a dozen of Ethernet Controller chips based on its patented hardwired TCP/IP
The unit price and performance of each chip were diversed by varying the number of sockets, the size of internal buffer memory and the host interface.
High price but high performance product is W5300.
W5300 supports 8 sockets, memory bus interface with 16 bit width data and 128KByte memory for internal rx/tx buffer. Due to these specification, host system can read from and write to the data buffer of W5300 inside in a very short access time, and can get the best throughput.
W5300 datasheet says that its maximum throughput is 80Mpbs.
In this post, I’d like to check what the real network performance of W5300 in off-the-shelf products is.
This summary was done with data which were collected on wiznetmuseum.com so far.
List of Products
There are 31 posts using W5300 on wiznetmuseum.com and only 8 posts among them have information like a kind of host device, system configuration, application type, etc.
Five among them are interfacting to W5300 with FPGA or DSP and the others are interfacing to with ARM7 or Cortex M3 MCU.
We can expect that using FPGA or DSP is for enhancing the access time to read/write data from/to W5300 because it can control the access time of BUS signal quickly.
ARM7 or Cortex M3 MCU also supplies fast access time throught raising clock speed.
Below table is the summary of posts according to host device and system clock value.
|Product Name||Host||System Clock||Source|
|W5300 Ethernet Module||DSP28335 (TMS320F28335)||Unknown||W5300 Ethernet Module on taobao.com|
|DSX50WZ||Xlinx XC3S50AN||50MHz||Digital Shortcut|
|V3 Core Board||STM32F207||120MHz||V3 Core Board on taobao.com|
|NIOS-II in FPGA||Altera Cyclone II||50MHz||W5300_report|
|Development Board Spartan-6||Xlinx XC6SLX9||50MHz||revsa.ir|
|AEPE-003||EP3C16Q240C8N (Cyclone III)||24MHz||ntrexgo.com|
Not all the post referred here has information of network throughput. Half of them, only four posts, have depictions about network performance even briefly.
The device the host of which is DSP28335 achieves up to 75Mbps throughput and it’s the best performance among them.
The second highest performance is the maximum 64Mbps and the device also uses FPGA, Xilinx XC3S50AN, as a host device. The application of this device is the web server and it can raise up to 64Mbps in using HTTP POST, up to 40Mbps in using HTTP GET.
There is no explanation why HTTP GET drops the performance 40%.
That’s it feels lack.
The device, Ginko iCore2, uses STM32F103 as MCU and it achieves up to 44Mbps.
The lowest performance among posts with performance information is 10.3Mbps that the device which embeds NIOS-II Core in Cyclone FPGA achieves. Even though it looks like interfacing to FPGA, as NIOS-II core controls the signals actually and so throughput dropped compared to others.
Below table is the summary of network performance information.
|Product Name||Maximum Throughput||Remarks|
|W5300 Ethernet Module||75Mbps||DSP28335와 Interfacing|
|DSX50WZ||64Mbps in HTTP POST
40Mbps in HTTP GET
|Gingko iCore2||44Mbps (5.5MByte/s)||EP4CE10F17C8, STM32F103 Dual Core|
|NIOS-II in FPGA||10.3Mbps||Cyclone II와 Interfacing|
To know what the maximum performance is with W5300 and what the condition is to achieve it, I investigated wiznetmuseum.com carefully but there was not obvious information and I couldn’t conclude.
But I’m sure that it is necessary to optimize the access time using FPGA or DSP to get the best performace of W5300.
And an example shows up to 75Mbps is possible.
If there is a chance, I expect to see data about what the access timing of bus signal for the maximum performance with W5300 is and what the maximum performance is then, and if it is impossible to achieve the theoritical maximum performance, what the reason is.
2019. 1. 15
James YS Kim