# W5100 vs W5100S – What diffenent, What enhanced, what new

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/w5100-vs-w5100s.png)

## Overview

[WIZnet](http://wiznet.io/) have launched [W5100S](https://www.wiznet.io/product-item/w5100s/) on May, 2018.

[W5100S](https://www.wiznet.io/product-item/w5100s/) is more enhanced than W5100 that is most popular. W5100S is lower heat, lower cost, higher efficient than W5100.
As above figure, Although the W5100S does not support PIN-to-PIN compatibility with the W5100 due to package changes, the LQFP48 & QFN48 package has been expanded to broaden the user’s choice.

On the other hand, it maintains FW compatibility with W5100, so it can use the W5100 user application without modification(except PPPoE), and it provides better network communication function by using new or improved functions.

Let’s look at how the W5100S differs from the W5100, what is improved, and what has been added compared to the W5100.

## Features

The following table shows the features of the W5100 and W5100S at a glance.

– Main Fetures

Main Features eng

– Host Interface

Host Interface eng

– Integrated 10Base-T/100Base-TX Ethernet PHY

Integrated 10Base-T eng

– Miscellaneous

Miscellaneous eng

## What is enhanced & What is new in W5100S.

For the sake of simplicity, we reviewed the features in the previous section.

Let’s take a closer look at the features that stand out from the W5100.

– Hardware

1. PIN (Package)

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/W5100_W5100S_Pin.png)

W5100S supports small package such as LQPF48 and QFN48 by removing ADDR [14:2], OPMODE[2:0] PIN of W5100 and optimizing power PIN.

Removed PINs have been replaced with register setting.

Note that the W5100S uses a core voltage of 1.2V rather than 1.8V.

2. Host Interface
* Parallel Bus Mode

Parallel Bus Access Timing has been improved. So Direct Bus Mode is eliminated and Indirect Bus Mode is only is supported.
The below figure shows comparision of write access timing.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/W5100_W5100S_WR_timing.png)

As shown in the figure, when the W5100S is operated at 100MHz, the bus access time is improved from 70ns to 40ns.

* SPI

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/w5100_W5100s_spi.png)

As shown in the figure, the W5100S supports up to 70MHz SPI Clock Speed.
Fast SPI is realized by improving 70ns clock speed of W5100 to 14.3ns

Note that T(DS) Time 7ns is required when W5100S SPI maximum clock is used.
The maximum continuos SPI clock speed that satisfies T(DS) is 43MHz (21.3 ns = 14.3 + 7).

* Interrupt

Interrupt occasionally is lost in W5100. In particular, the interrupt pin is kept low by the overlap interrupt generated at the same time as RX Interrupt clear, so that the HOST can not recognize the interrupt occurrence any more.

In order to compensate for this, W5100S reproduces RX interrupt when RX buffer is left after RECV Command execution, and reproduces interrupt when interrupt remains after interrupt pend timing even if overlap interrupt occurs.

For more detalis, Refer to [wizwik](https://wizwiki.net/wiki/lib/exe/fetch.php?media=products:w5100s:application:w5100s_an_interrupt_v100e.pdf).

– TCP

1. PSH Flag

The PSH flag informs the application that the TCP data has been received, and the application has a function to process data quickly.

If both W5100 and W5100S transmit data larger than MSS, PSH flag is set to the last data divided by MSS unit.

The W5100S sets the PSH flag in the transmission packet that makes the other party’s window zero, even if it is not the last packet, and allows the application to receive it fast.

Unlike the W5100, W5100S can set all transmit data packet when the Sn_MR2[BRDB] = ‘1’ .

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/TCP-flag.png)

2. RST Block

W5100S can block to transmit a RST packet in order to protect on a port scan attack when MR2 [NOTCPRST] = ‘1’.

Also, when running application such as Web Server, it may not be convenient to communicate with the Web browser due to the limited number of SOCKET(maximum 4).

If web brower request a content when no more listen SOCKET, then web browser receive a RST packet and doesn’t request again the contents.

The RST packet block allows the Web browser to request the content agian and receive it when the connected SOCKET is change to the listen.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/TCP-RST-block.png)

3. Auto Keep Alive

W5100 can manually send a Keep Alive Packet by using SEND_KEEP command of Sn_CR. Also W5100S can automatillcaly send a Keep Alive Packet every Sn_KPALVTR time.

SEND_KEEP can only be performed while Sn_KPALVTR is zero.

– UDP
1. WOL

W5100S supports WOL that can analyze the specified magic packet received through UDP and wake up a standby HOST system.

When receiving a WOL magic packet, IR2[WOL ] is set and an interrupt occurs.

2. ICMP(Port Unreachable) Block

W5100 and W5100S transmit ICMP (Port Unreachable) message when UDP packet is received to port that is not opened. Like TCP, UDP can also be target to port scan attacks.

W5100S can block a ICMP (Unreachable Port) message transmission and protect from Port Scan Attacks when MR2[UDPURB] = ‘1’.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/ICMP-block.png)

3. Broad/Uni/Multicast packet filtering

W5100 receives a unicast packt as well as un-wanted packet such like as broadcast and multicast packet though the opened UDP port. So, If you receive unwanted packets, you must receive them and discard them.

But, W5100S can block to receive them by configuration as follows. So, You can filter out the un-wanted packets.

The UDP Filter function can be set as follows.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/UDP-Filter.png)

– MACRAW

When MACRAW SOCKET is used, W5100 receives the packet sent to itself as well as both broadcast and multicast packet. If the received packet is not needed, there is a burden to the user to directly receive and discard.
W5100S discards not only unnecessary broadcast, multicast packet but also IPv6 Packet by filtering without any reception of user.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/MAC-Filter.png)

– PPPoE

The W5100’s PPPoE is implemented as hardwired logic, which means it can not handle various options such like as other than PAP/CHAP encryption while processing the PPPoE connection.

W5100S enhanced the flexibility of option processing by processing the PPPoE connection with software using MACRAW SOCKET, and implemented only the repetitive LCP-ECHO transmission to maintain the connection and termination recognition as hardware logic.

For more details, Refer to [wizwiki](https://wizwiki.net/wiki/doku.php?id=products:w5100s:application:pppoe).

– Retransmission Configuration

Unlike W5100, W5100S can set retransmission time by SOCKET through Sn_RTR & Sn_RCR register.
The existing RTR & RCR Register has been changed to set the initial value of Sn_RTR & Sn_RCR .
That is, If you does not set to Sn_RTR & Sn_RCR, SOCKET retransmission time is configured by RTR & RCR.

– SOCKET-less Command

W5100S provides the function to send ARP and PING request to destination without using SOCKET.

This function is controlle as follow through SLCR (SOCKET-less Command), SLIR (SOCKET-less Interrupt), SLIMR (SOCKET-less Interrupt Mask), SLIRCLR (SOCKET-less Interrupt Clear), SLDIPR (SOCKET-less Destination IP Address), SLDHAR (SOCKET-less Destination Hardware Address), PINGIDR (PING ID), PINGSEQR (PING Sequence Number) registers.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/SOCKETless_Command.png)

1. ARP

2. PING

– PHY
1. Operation Mode

W5100 controls the PHY operation mode by controlling Hardware PIN OPMODE [2: 0], and operation mode can not be set after reset.

On the other hand, W5100S can set operation mode after reset through PHYCR0 regsiter.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/PHYCR0.png)

2. MDC/MDIO Controller

W5100S has a built-in MDC/MDIO controller to control the internal registers of the Ethernet PHY such as BMCR and BMSR.

MDC/MDIO Controller consists of PHYRAR (PHY Register Address), PHYDIR (PHY Data Input), PHYDOR (PHY Data Outuput), PHYACR (PHY Access Control) register.

For more details, Refr to [wizwiki](https://wizwiki.net/wiki/lib/exe/fetch.php?media=products:w5100s:w5100s_ds_v123e.pdf).

3. Power Down Mode

The W5100S supports the Power Down Mode of the Ethernet PHY.

Note that the Power Down Mode setting changes the system clock to 25MHz, so the W5100S SPI or BUS access time is adjusted to 25MHz.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/PHYCR1.png)

– System Clock Switching

The W5100S can be used with a system clock of 100MHz or 25MHz.

Note that the Ethernet Power Mode setting automatically changes to 25 MHz.

![](https://wiznetmuseum.com/wp/wp-content/uploads/2019/02/Clock_switching.png)

– Configuartion Lock

W5100S provides the Lock function for the following three settings to prevent unintended setting changes.

1. Clock Switching : MR2[CLKSEL]

2. Network Inforamtion

Network information registers such as GWR, SIPR, SUBR,SHAR, SIPR

3. PHY Control : PHYCR0, PHYCR1

## Conclusion

So far, we have looked at the distinctive features of the W5100S.

Not only for the existing W5100 users, but also for the new W5100S users, I hope that the W5100S will become another best seller such like as W5100.

#####Curator: MC
#####Email: mc@wiznet.io